Phase-locked loop circuits are widely used in electronic systems. These circuits are used to generate an accurate replica of an incoming signal. For example, in a computer, a phase-locked loop is used by a microprocessor to generate an on-chip clock signal from an off-chip clock signal.
FIG. 1 is a generalized illustration of a typical phase-locked loop circuit 20. The circuit 20 includes a phase detector 22 that receives a reference signal and a feedback signal as inputs. The phase detector produces a phase error signal corresponding to the difference in phase between the reference signal and the feedback signal. The phase error signal is processed by a charge pump 24 to provide a pulsed error signal corresponding to the phase error signal. The pulsed error signal is applied to a capacitor 26. The charge supplied by the pulsed error signal develops a control voltage on capacitor 26. The control voltage stored on the capacitor 26 is then used to control the frequency of the output signal of a voltage controlled oscillator (VCO) 28. More particularly, the output signal is controlled to reduce any difference in phase between the reference signal and the feedback signal. The output signal may then be re-processed as a feedback signal for the phase detector 22.
The present invention is directed toward an improvement in existing phase detectors 22. FIG. 2 illustrates a typical prior art digital phase detector 22. The phase detector 22 includes a signal lead portion 30 and a signal lag portion 32, the outputs of which are fed to a reset circuit 34. The phase detector 22 of FIG. 2 is implemented with NOR gates, however other configurations, such as NAND gates, may also be used.
The signal lead portion 30 generates a lead output signal on lead output line 36 when the reference signal is faster (leading) than the feedback signal. The signal lag portion 32 generates a lag output signal on lag output line 38 when the reference signal is slower (lagging) than the feedback signal. The lead output line 36 and the lag output line 38 are connected to a charge pump 24, as shown in FIG. 1.
The signal lead portion 30 and the signal lag portion 32 each function as a pair of latches. In the signal lead portion 30, logic gates 40 and 42 function as a first latch 43 and logic gates 44 and 46 function as a second latch 47. Similarly, in the signal lag portion 32, logic gates 50 and 52 function as a third latch 53 and logic gates 54 and 56 function as a fourth latch 57.
The reset circuit 34, implemented as a four input NOR gate in FIG. 2, is used to reset the four latches (43, 47, 53, 57) after the signal lead portion 30 has detected an edge of a reference signal or the signal lag portion 32 has detected an edge of a feedback signal. The reset output line 60 is connected to each of the four latches (43, 47, 53, 57). When the input lines (62, 64, 66, and 68) to the reset circuit 34 are all low, the reset circuit 34 generates a digital high signal on reset output line 60. This signal resets the four latches (43, 47, 53, 57) of the phase detector 22.
Unfortunately, there is no guarantee that the signal lead portion 30 and the signal lag portion 32 of the phase detector 22 will take the same amount of time to reset. If for example, the signal lead portion 30 should reset before the signal lag portion 32, inputs 62 and 64 will go high before inputs 66 and 68. Once input 62 or 64 goes high, the reset circuit 34 will generate a low signal, thereby de-asserting the reset signal before the signal lag portion 32 has been properly reset. A new sample interval for the phase detector 22 begins when the phase detector reset signal is de-asserted (digital low). Therefore, a phase detector circuit that uses a standard logic gate for the reset circuit 34 is vulnerable to a latch race condition that could cause the phase detector to start sampling inputs before all parts of the phase detector circuit 22 have been reset. More particularly, a latch race condition can preclude all latches in a phase detector 22 from being properly reset.
The reference signal into a phase detector 22 of a phase locked loop 20 may include noise that is erroneously interpreted by the latch 30 as a change in signal state, causing the phase detector 22 to malfunction. It would be highly desirable to provide a reset circuit of a phase detector in a phase-locked loop that is immune from signal noise that erroneously causes a latch setting operation. Further, it would be highly desirable to provide a reset circuit of a phase detector in a phase-locked loop that is not subject to latch race conditions that prevent the resetting of all latches in a phase detector.